1. Field of the Invention
The present invention provides ESD (electrostatic discharge) protection circuits and related techniques, and more particularly, a kind of simplified layout to effectively realize the ESD protection circuits and related techniques.
2. Description of the Prior Art
A typical chip is equipped with conductive pads to receive external power potentials and to exchange data with other external circuits/chips. For instance, the chip is equipped with power pads and ground pads to transmit the positive or negative voltage and the ground voltage to the power supplies. Similarly, the chip is also equipped with signal input/output pads (I/O pads) to receive input signals and to transmit output signals.
However, when an ESD event happens, such as human bodies or manufacturing machines accidentally contacting the pad of a chip, the massive electrostatic currents of the ESD power source flow through the pad into the chip. If the circuit structure within the chip is overloaded with the current, it would be burned down and be unable to work normally. Thus, each pad of the chip is generally equipped with an ESD protection circuit. The basic function of the ESD protection circuit is to serve as a conductive path with low impendence between the two pads, so that ESD currents pass by this path instead of other internal circuits of the chip. In this way, the circuits in the chip are protected from ESD events. It is equivalent that the ESD protection circuit shorts the two pads to guide ESD currents into the bypass path instead of the internal circuits in the chip. But, during the regular operation of the chip, the ESD protection circuit turns the current path between the two pads off to avoid interfering in the regular operation of the chip.
In other words, the ESD protection circuit itself distinguishes between an ESD event and the regular operation of the chip in order to avoid activating at incorrect time. To differentiate the two conditions above, the ESD protection circuit determines if it is the normal power-on procedure or an ESD event according to the rising time of the voltage of the pad. During an ESD event, the ESD power source usually leads to the rapid rising of the voltage of the pad, and the rising time of the voltage is about 10 to 100 ns (ns, 1 ns=10−9 s). In regular power-on procedure, the voltage of the pad (such as the power pad) rises slower, in which the rising time usually falls on the level of ms (ms, 1 ms=10−3 s). According to the difference of the rising time of the voltage, the ESD protection circuit distinguishes between an ESD event and the regular power-on procedure.
According to the theory above, when the conventional techniques provide a specific pad (such as a power pad), the conventional ESD protection circuit connects a resistor and a capacitor in series to the pad to form a RC network for differentiating different rising times of the voltage of the pad and for determining if an ESD event happens. When an ESD event happens on the protected pad, the voltage of the specific pad rises rapidly, and the rising time of the voltage is lower than the time constant of the RC network (the time constant is the product of capacitance of the RC network and resistance of the RC network). Thus, the RC network does not respond in time to the ESD event, so that the transient voltage of the capacitor keeps steady and the transient difference in voltage across the resistor is rising as the voltage of the specific pad. By the RC network, the conventional ESD protection circuit triggers the ESD clamp circuit to turn on a conductive path for bypassing the ESD current of the protected pad. However, the voltage of the specific pad rises slowly, and the rising time is more than the time constant of the RC network during the regular operation and the power-on procedure of the chip. Thus, the RC network responds to the ESD event in time, and the difference in voltage across the resistor is steady and the difference in voltage across the capacitor is increased as the voltage of the specific pad. Thus, the ESD clamp circuit is turned-off to avoid interfering with the regular operation of the chip.
However, there are disadvantages of the conventional techniques described above. One of the disadvantages is using more layout area. To form the RC network for differentiating between ESD event and the regular operation, the conventional ESD protection circuit is realized with capacitors and resistors of great value, which uses a great deal of layout area. Generally, the time constant of the RC network is about 150 ns to 200 ns in order to differentiate between an ESD event and the regular operation so that big capacitors are necessary. Thus, the conventional ESD protection circuit uses a great deal of layout area, which is a disadvantage of the chip density and increases the cost of chip design.